1.) Field of the Invention
The present invention relates to a ferroelectric memory device, and more particularly a ferroelectric memory device suitable for a 1T-1C type memory which forms one memory cell by using one transistor and one ferroelectric capacitor, and to a method of driving a 1T-1C type memory.
2.) Description of the Related Art
A ferroelectric capacitor made of ferroelectric material interposed between a pair of electrodes produces polarization in an amount corresponding an applied voltage. The characteristics of a polarization amount relative to an applied voltage show hysteresis, and even if the applied voltage is turned off, there remains residual polarization. If residual polarization is formed corresponding in amount to input data, a non-volatile memory can be formed by using the ferroelectric capacitor. For example, an insulated-gate field effect transistor can be turned on or off in accordance with polarization of a ferroelectric capacitor whose one electrode is connected to the insulated gate of the transistor.
Products of a 2T-2C type ferroelectric random access memory (FeRAM) using two transistors and two capacitors per one memory cell are now available up to 64 k bits. However, a 1T-1C type FeRAM using one transistor and one capacitor per one memory cell is still under the development stage for practical application.
FIGS. 8A to 8C show a ferroelectric capacitor according to conventional techniques. As shown in FIG. 8A, on the surface of a p-type silicon substrate 51, a floating gate electrode 53 of polysilicon or the like is formed, with a gate oxide film 52 being interposed between the substrate and the floating gate electrode. On this floating gate electrode 53, a ferroelectric layer 54 is formed, and on this ferroelectric layer 54, a control gate electrode 55 is formed. This lamination structure is patterned to form a gate electrode. A source region 61 and a drain region 62 are formed on both sides of the gate electrode by doping n-type impurities through ion implantation.
Consider that a positive voltage +V is applied to the control gate electrode 55 and thereafter this voltage is turned off. Upon application of a voltage of +V, the ferroelectric layer 54 induces polarization as shown in FIG. 8A. This polarization remains and becomes residual polarization even after the applied voltage to the control gate electrode 55 is turned off. The residual polarization charges the floating gate electrode 53 positive and induces an n-channel 60 in the surface layer of the p-type silicon substrate 51. The source region 61 and the drain region 62 are therefore electrically connected via the n-channel 60.
As shown in FIG. 8B, consider that a negative voltage -V is applied to the control gate electrode 55 and thereafter this voltage is turned off. Upon application of a voltage of -V, the ferroelectric layer 54 induces polarization of a polarity opposite to that shown in FIG. 8A. This polarization remains and becomes residual polarization even after the applied voltage to the control gate electrode 55 is turned off. The residual polarization charges the floating gate electrode 53 negative and extinguishes the channel in a surface layer of the p-type silicon substrate 51. The source 61 and the drain 62 are therefore electrically cut off.
In the above manner, data can be stored in a non-volatile way by making the applied voltage to the control gate electrode 55 relative to the substrate 51 control the polarization of the ferroelectric layer 54.
The ferroelectric memory shown in FIG. 8C has a series circuit of a capacitor C2 and a capacitor C1, the former utilizing the gate oxide film 52 as the capacitor dielectric layer and the latter utilizing the ferroelectric layer 54 as the capacitor dielectric layer. Since the dielectric constant of the ferroelectric layer 54 is considerably higher than that of the gate oxide film 52, the capacitance of the capacitor Cl tends to be larger than that of the capacitor C2.
As shown in FIG. 8C, as a voltage V is applied across the substrate 51 and the control gate electrode 55, a voltage V1 across the ferroelectric capacitor C1 become less than a voltage V2 across the series connected capacitor C2.
If the hysteresis characteristics of the ferroelectric capacitor require the voltage V1, a large voltage of V1+V2 is required to be applied to the control gate electrode 55.